what is the difference between vhdl language and verilog language?

Question

what is the difference between vhdl language and verilog language?

Answer 1

VHDL is loosely based on ADA which was also developed for use by the US DoD, and is a purely behavioral language. Verilog evolved from a gate level simulator to combine behavioral code and built-in primitives (its language roots are not obvious, but it is fairly simple compared to VHDL).



The gate/primitive behavior in Verilog is generally consistent with respect to how hardware works, but VHDL has dysfunctional semantics. For that reason Verilog is generally used for final chip verification in preference to VHDL. VHDL is more expressive, so works better for design definition (presynthesis), and OK for logic with no bidirectional components (e.g. FPGAs).



Recent additions to Verilog through SystemVerilog have all the complexity and dysfunctionality of VHDL. Both SystemVerilog and VHDL are IEEE standards, Verilog was originally an Accellera standard but departed after spinning off Verilog-AMS (still at Accellera).



Note: both these languages are ~ 30 years old and barely adequate for designing/verifying designs on 22nm Silicon. Most of the recent OO additions would be better left in C++ or Java.

Answer 2

VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits.



In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL, not to be confused with VHDL (a competing language), is most commonly used in the design, verification, and implementation of digital logic chips at the register transfer level (RTL) of abstraction. It is also used in the verification of analog and mixed-signal circuits.

Answer 3

Verilog Wiki

Answer 4

http://en.wikipedia.org/wiki/VHDL

http://en.wikipedia.org/wiki/Verilog